1. Field of the Invention
This invention relates to a power select circuit well adapted for an electronic device using a semiconductor integrated circuit, such as an IC card selectively driven by two power supply systems, an internal power source and an external power source.
2. Description of the Related Art
The IC card is selectively driven by an internal power source at 3 V and an external power source at 5 V. When the 5 V external power source is not supplied, the IC card is driven by the 3 V power source. When the external power source is supplied, a power select circuit operates to stop the power supply by the internal power source, and the IC card is driven by the external power source.
FIG. 1 shows a circuit diagram of a conventional power select circuit. In the figure, node 1 is connected to external power source 21 at 5 V via switch 20. Node 2 is always coupled with internal power source 22 at 3 V. Node 1 is connected to ground potential via resistor 9. Nodes 1 and 2 are respectively connected to the noninverting input terminal and the inverting input terminals of differential input section 15 in voltage comparator 10. Voltage comparator 10 contains bias generator 14, and output amplifier 16, and differential input section 15 and output amplifier 16 are driven by the output bias of bias generator 14. Node 1 is connected to output node 3 via MOSFET 7. Node 2 is connected to output node 3 via MOSFET 8. Semiconductor circuit 24 is connected between node 3 and ground, with a capacitor 23 connected in parallel therewith to stabilize the output voltage. The output signal of voltage comparator 10 is supplied to the gate of MOSFET 7 via inverter 11, and further connected to the gate of MOSFET 8 by way of inverter 12.
When a voltage at 5 V is supplied to node 1, from external power source 21, high logical level "1" appears at the input of inverter 11, because the plus input of voltage comparator 10 is at 5 V, and the minus input of the same at 3 V. Therefore, MOSFET 7 is turned on, while MOSFET 8 is turned off. Semiconductor circuit 24 is energized by external power source 21 at 5 V. When switch 20 is turned off, node 1 is at ground potential, and the output logical level of voltage comparator 10 is "0". Then, MOSFET 7 is turned off, while MOSFET 8 is turned on. As a result, semiconductor circuit 24 is energized by internal power supply 22.
FIG. 2 shows a set of waveforms useful in explaining the operation of the circuit of FIG. 1. This chart illustrates voltage variations at the nodes when switch 20 is sequentially turned on, off and on. Let us look at the voltage at output node 3 during period T6 when switch 20 is in an off state (see FIG. 2). Since node 3 is for supplying the positive electric power to semiconductor circuit 24, it is necessary to take some measure to stabilize the voltage. To this end, this instance uses stabilizing capacitor 23. During period T6, the voltage of node 3 should be maintained at 3 volts. The voltage, however, drops below 3 volts which is supplied from internal power source 22. This is because MOSFET 8 is in an off state during period T6. For this reason, there is a danger that since the power voltage drop is excessive, semiconductor circuit 24 for receiving the power from node 3 may operate erroneously. For example, if the data stored in the memory of semiconductor circuit 24 is destroyed, the detriment is serious even after period T6 terminates, and the potential at node 3 is restored to 3 V. The delay of turning on of MOSFET 8 is due to the presence of a total of response times (T3+T4+T5) between the input and the output of voltage comparator 10, and inverters 11 and 12. The larger this response time, the lower the minimum voltage at node 3. This is an undesirable matter (First problem).
Let us consider period T7 from an instant that switch 20 is turned on till MOSFET 8 is turned off, when switch 20 is switched from off state to on state. During this period T7, a DC current flows into the path including nodes 1, 3 and 2, via a parasitic diode in P channel MOSFET 7 and turned-on MOSFET 8. This current is a reverse current for internal power source 22, possibly deteriorating the battery 22.
This current flow is caused by the turn-on delay of MOSFET 8 and by the delay of input/output response periods T3', T4' and T5' of voltage comparator to and inverters 11 and 12. When this input/output response period increases, the current flowing period in the reverse direction increases, thereby resulting an insufficient operation. Particularly, in the case of the IC card, the battery as the power source must be continuously used for at least 2 to 3 years. In this respect, it is undesirable that the circuit involves some cause for the battery deterioration (Second problem).
A fixed current as a bias current constantly flows in voltage comparator 10. It is preferable to minimize this. Because, as noted above, the power consumption of the battery used in the IC card should be minimized for using the IC card for at least two or three years without changing the battery. However, a necessary amount of current consumption is indispensable for the normal operation of the voltage comparator. (Third problem).
To solve the first and second problems, it is necessary to speed up the operation of inverters 11, 12 and voltage comparator 10. To this end, parasitic capacitive loads appearing at the respective nodes in voltage comparator 10 and an output node thereof should be driven by a large amount of current, which is realized by increasing a bias current usually flowing in voltage comparator, or by enlarging the gate width of an MOSFET. The operation speed of inverters 11 and 12 can be increased by enlarging the gate width of MOSFETs forming these inverters. The above mentioned solution, however, further promotes the third problem.